I am an Assistant Professor in the Department of Computer Engineering at the Rochester Institute of Technology (RIT). My research centers on hardware security with an emphasis on provably secure system design and design automation algorithms. Prior to my academic career, I researched high-frequency, wide-band digital signal processing system architecture at the U.S. Naval Research Laboratory where I served as the lead digital designer for a currently-fielded naval system. I have published more than 20 peer-reviewed publications, two of which have been nominated for Best Paper, including most recently at the 2021 Design Automation Conference (DAC). I have been recognized as an ARCS Scholar, a Future Faculty Fellow, and an Edison Memorial Graduate Fellow. I received my PhD in Electrical Engineering from the University of Maryland, College Park in 2022.

Research Focus

Primary Research Areas: Hardware Security, Digital VLSI/CAD, and Computer Architecture

My research centers on the design of secure, trustworthy, and reliable electronic systems with an emphasis on hardware security, design automation, and artificial intelligence. Currently, I am working to address the security ramifications of outsourcing integrated circuit (IC) fabrication to untrusted manufacturing facilities. Such outsourcing enables companies to obtain high-end performance at a modest cost, but exposes the entire design of an IC to potentially malicious facilities, raising concerns of intellectual property (IP) piracy, reverse engineering, and malicious hardware modification. My work in this domain uniquely explores solutions with a focus on provable, system-level security guarantees, ranging from security-aware design automation algorithms that optimally construct architectures to the theoretical modeling of hardware security guarantees. At the core of all of my work is the use of deep and rigorous mathematical analysis and modeling.

Thanks to Our Sponsors!