Design Space Modeling for Logic Obfuscation to Enable System-Wide Security during IC Manufacture and Test
About:
Due to the rising cost of semiconductor manufacturing, computer chip designers are increasingly reliant on offshore manufacturers. These manufacturers are generally considered to be untrusted, driving concerns of intellectual property (IP) piracy and theft. Logic obfuscation, also called logic locking, was developed to mitigate these threats, however, its effectiveness varies widely based on how obfuscation resources are allocated throughout a system. This project studies how to model, automate, and evaluate the high-level configuration of logic obfuscation in a system to maximize security with minimal design overhead. The project's novelties are the system-wide view of the obfuscation resource allocation problem and the framework to generate mathematical models for this allocation problem. The purpose of these models is to automatically identify effective distributions of budgeted obfuscation resources in varied computer chips and provide intuition on how obfuscation secures a complex system. The project's broader significance and importance are in lowering the barrier to developing secure computer chips for high-trust applications (e.g., healthcare, defense, finance, and automotive) through automation. The integration of education and research is a key objective. This includes research opportunities for graduate and undergraduate students as well as open-source course modules to train next-generation security experts for the workforce.This project bridges the knowledge gap between combinational, gate-level logic obfuscation schemes and their security impact in the larger integrated circuit they protect. Specifically, the project develops a design space modeling framework for logic obfuscation system configuration in order to budget obfuscation resources, allocate resources to design regions, and specify obfuscation schemes in these regions. Given a fixed budget of various obfuscation resources, these models automatically identify obfuscation configurations that fulfill system-wide security goals with minimal design overhead. The research artifacts are 1) quantifiable system security metrics for obfuscation, 2) an open-source design space modeling framework for obfuscation, and 3) a verification of generated models.
Publications:
- Wojtal, Thomas and Zuzak, Michael "Mitigating Electro-Optical Frequency Mapping Attacks on Logic-Locked Integrated Circuits" Springer Journal of Hardware and Systems Security (JHASS) , 2025 https://doi.org/10.1007/s41635-025-00158-w
- Lam, Long and Melnyk, Maksym and Zuzak, Michael "Low Overhead Logic Locking for System-Level Security: A Design Space Modeling Approach" IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED) , 2024 https://doi.org/10.1145/3665314.3670833
- Nakano, Katsuaki and Zuzak, Michael and Merkel, Cory and Loui, Alexander "Trustworthy and Robust Machine Learning for Multimedia: Challenges and Perspectives" IEEE International Conference on Multimedia Information Processing and Retrieval (MIPR) , 2024
- Zuzak, Michael and Liu, Yuntao and Srivastava, Ankur "Security-Aware Resource Binding to Enhance Logic Obfuscation" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , v.42 , 2023 https://doi.org/10.1109/TCAD.2023.3294453
- Xu, Hongye and Liu, Dongfang and Merkel, Cory and Zuzak, Michael "Exploiting Logic Locking for a Neural Trojan Attack on Machine Learning Accelerators" GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023 , 2023 https://doi.org/10.1145/3583781.3590242
Open-Source Tooling:
Design Space Modeling for Logic Locking:
DSM for Logic Locking is an open-source example script implementing Design Space Modeling for obtaining a satisfying locking configuration given an arbitary IC. It provides a means for Python users to utilize R functions, specifically SSANOVA modeling, while staying in the Python domain. An overview of the design space modeling algorithm can be found in the ISLPED'24 paper linked above.Adjoining Gates:
The Adjoining Gate system is an open-source set of functions to detect any leakage of logic locking keys from electro-optical frequency mapping and automatically implement Adjoining Gates as a countermeasure in logic-locked circuits. An extensive overview of the Adjoining Gate technique can be found in the JHASS'25 paper linked above.RenCTF Gamified Security Workforce Development Platform:
RenCTF is an interactive, team-based platform designed to teach penetration testing (pentesting) skills. Combining web application functionality with hardware integration, RenCTF provides a unique and engaging experience for participants. This project was developed by RenAaron Ellis and Dr. Zuzak.
Graduate Thesis:
Long Lam:
Thomas Wojtal:
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